N200 Series Ultra-Low Power RISC-V Processor
N200 Series is designed for deeply embedded application with low power and area consumption, for AIoT and
general MCU domains with state-of-art features, perfectly for the replacement of ARM Cortex-M0/M0+/M3/M23.
N200 Core
JTAG/
-Wires JTAG
WFI/WFE
DEBUG
ECLIC
2
NICE
TIMER
Ultra-Low
Power
RV32
I/E/M/A/C
2
-stage Pipeline
Machine, User, Security (PMP, TEE)
Supervisor-Mode
N200 uCore
PMP
ILM
TEE
DLM
APB
MUL/DIV
I-Cache
Fast-IO
RISC-V
Standard Debug
3
2-bit AHB-Lite &
4
-wire &
Low Latency Full Development
3
2-bit APB
2
-wire JTAG
Interrupt
Toolkit
AHB-Lite
N200 Series Ultra-Low Power RISC-V Processor
N200 Series is highly configurable, allowing customers to add or remove hardware feature to optimize the performance,
power, and area of each processor instance on their SoC. Here are 3 typical configurations.Detailed Introduction>>>
Comparisons to Cortex-M3
Comparisons to Cortex-M0/M0+
Comparisons to Cortex-M23
•
•
RV32 IMC/EMC supported
Key configurations
• RV32 IMAC/EMAC supported
• Key configurations
• RV32 IMAC/EMAC supported
• Key configurations
•
•
•
•
User mode & PMP
• User mode & PMP
• User mode & PMP
Hardware Multiplier/Divider
NICE Interface for extension
Fast-IO IF
• Hardware Multiplier/Divider
• NICE Interface for extension
• Fast-IO IF
• Hardware Multiplier/Divider
• NICE Interface for extension
• Fast-IO IF
•
ILM and DLM
• ILM and DLM
•
•
Supervisor mode
S-PMP TEE
N200 Series Ultra-Low Power RISC-V Processor
Lowe-power design is the key mind during N200 Series’micro-architecture implementation, also including efficient
instruction fetch unit, low-latency interrupt handler, etc. for the best PPA optimization. Here is the PPA comparison
between Nuclei N205 and ARM Cortex M3.
Dhrystone
DMIPS/MHz)
CoreMark
CoreMarks/MHz)
Area
(K Gates)
Dynamic Power
(
(
(
mA)
1.415799
3.346419
36
3.32
33.96
27
18.9
1.25
Nuclei N205
ARM Cortex-M3
Apple-to-apple comparison on a customer’s chip under the same conditions
ISA
Timer
•
RISC-V RV32 E/I/M/A/C ISA supported
Configurable 64-bit private timer
CPU Core
•
•
•
2-Stage Pipeline
Interrupt
ECLIC（Enhanced Core Level Interrupt Controller）
Configurable Branch Prediction unit
Configurable Prefetch Unit
•
RISC-V standard interrupts supported, including software,
timer and external interrupts
Privileged
Modes
•
•
•
Machine-Mode supported
User-Mode supported
• Configurable interrupt numbers, levels and priorities.
Interrupts and priorities are also programmable during
run time
Supervisor-Mode supported
I-Cache
• Vectored fast interrupts supported
•
Configurable Cache size, 2-way, Cache Line Size 32Bytes
•
•
Nested interrupts supported
Bus Interfaces
•
•
•
•
32-Bit AHB-Lite System Bus Interface
32-Bit APB PPI (Private Peripheral Interface)
32-Bit ILM, DLM Bus Interface
Interrupt tail-chaining supported
NMI
•
•
NMI (Non-Maskable Interrupt) supported
32-Bit Fast-IO Interface
NICE
Extension
Allowing customers to add user-defined instructions
Debug
•
•
4-wire & 2-wire JTAG supported
Configurable Hardware Breakpoints
• Implementing application specific hardware co-unit
based on NICE interface
Safety
•
•
(
Dual Core Lock-Step (separate license)
Parity/ECC protection on Memory/Bus interfaces
separate license)
Security
•
•
•
Configurable PMP (Physical Memory Protection) feature
Configurable TEE (Trusted Execution Environment) feature
Configurable SCP (Side Channel Protection) feature
separate license)
Tool Kit
•
•
Standard RISC-V Toolchain supported
Linux/Windows IDE (Integrated Development
Environment) supported
(
Low Power
•
•
WFI（Wait For Interrupt）and WFE（Wait For Event）Supported
Sleep and Deep Sleep Mode Supported
N200 Series Diagram
JTAG
DEBUG
Core Wrapper
TIMER
…
Core
Extend
Instructions
ECLIC
IRQ
Misc Ctrl
NICE IF
NMI
N200 Series uCore
D-IF
I-IF
LM Ctrl
BIU
System Bus IF
(AHBLite)
Fast-IO IF
(Single-Cycle)
ILM Master IF
(AHBLite/SRAM)
LM Master IF
(AHBLite/SRAM)
Private Peripheral IF
(APB)
Fast-IO
Modules
Peripheral Bus
System Bus
ILM
DLM
Ext
MEM
Per
1
Per
2
Per
3
SRAM