N100Extreme-Low Power RISC-V Processor  
N100 series is designed for extreme-low power applications. It’s our smallest core and is perfect  
for the traditional 8-bit and 16-bit 8051 upgrading. Detailed Introduction>>>  
N100 Core  
JTAG/  
-Wires JTAG  
2
9
K
IRQC  
TIMER  
DEBUG  
Gate count  
9K  
Machine Mode  
20-bit  
Address Space  
2
-Stage Pipeline  
<
RV32EC  
N100 uCore  
AHB-Lite  
RISC-V  
Standard Debug  
4-wire and  
2-wires JTAG  
Full Development  
Toolkit  
Low Latency  
Interrupt  
3
2-bit AHB-Lite  
ISA  
RISC-V RV32 E/C ISA supported  
2-Stage Pipeline  
CPU Core  
Privileged Modes  
Machine Mode only  
Addressing  
20-bit instruction and data addressing width, supporting 1M  
memory space  
Bus Interface  
Debug  
32-Bit AHB-Lite System Bus Interface  
MCU  
RISC-V External Debug Support Version 0.13” supported  
4-wire & 2-wire JTAG supported  
MCU  
Sensor  
Configurable Hardware Breakpoints  
N101 is a typical  
configuration of N100  
series, which is perfect  
for ultra-low power  
applications.  
Low Power  
WFIWait For Interruptand WFEWait For Event)  
Supported  
Toys & some  
home appliances  
Metering  
Sleep and Deep Sleep Mode Supported  
Timer  
Configurable 64-bit private timer  
Interrupt  
Core Priviate Interrupt Controller (simplified version of ECLIC,  
Enhanced Core Level Interrupt Controller)  
Timer and external interrupts supported  
Configurable interrupt number  
Vectored fast interrupts supported  
Tool Kit  
Standard RISC-V Toolchain supported  
Linux/Windows IDE (Integrated Development Environment)  
supported  
N100 Series Diagram  
JTAG  
DEBUG  
Core Wrapper  
Core  
TIMER  
IRQC  
IRQ  
N100 Series uCore  
BIU  
System Bus IF  
(AHBLite or ICB)  
System Bus  
Ext  
MEM  
SRAM