9
00-MC High Performance SMP Multi-Processors  
Configurable 1~16 Cores, synchronous (with  
Multi Core Debug Module  
PLIC  
Timer  
different clock ratios) or asynchronous clocks  
supported  
Core <0>  
VPU  
VPU  
Core <n-1>  
I/D Cache  
FPU  
MOSEI - cache coherency protocol supported  
I/D Cache  
FPU  
I/DLM  
MNU  
DSP  
I/DLM  
MNU  
DSP  
Configurable Snoop Fliter SCU  
Configurable size Cluster Cache  
PMP  
PMP  
Cache line Size configurable as 32/64-Byte  
Configurable way set as 8/16  
AXI4  
AXI4  
IOCP  
IOCP  
Snoop  
Filter  
Snoop Control  
Unit  
Configurable cycle counts of Tag RM and Data  
RAM  
Cluster Cache  
Cluster Bus Interface Unit  
Configurable 1-16 IO coherency ports (IOCP)  
AXI4  
AHB-Lite  
Cluster Memory Ports  
Cluster Memory Ports